1. Field of the Invention
The present invention relates to a semiconductor memory device that generates a startup timing of an amplifier circuit using a dummy circuit.
2. Related Background Art
In conventional semiconductor memory devices, various methods have been considered to generate a startup signal of an amplifier for amplifying data read out from a memory cell by using a dummy memory cell so as to allow a startup timing of the amplifier to follow precisely the fluctuations in memory-cell reading-out timing caused by a process, a voltage and the like.
As a configuration example of the conventional semiconductor memory devices, FIG. 15 to FIG. 18 schematically show circuit configurations disclosed in “IEEE JOURNAL OF SOLID-STATE CIRCUITS, November 2001, Vol. 36, No. 11, pp. 1738-1744) and U.S. Pat. No. 6,212,117.
In FIG. 15, reference numeral 500 denotes a memory array, 501 denotes an edge column (optical dummy column) included in the memory array 500, 502 denotes a dummy column included in the memory array 500 and 504 denotes a plurality of normal columns included in the memory array 500, respectively. Herein, the normal columns refer to those columns other than the edge column and the dummy column.
Furthermore, reference numeral 505 denotes a dummy control circuit connected to the memory array 500, 507 denotes an amplifier control circuit to which an output signal from the dummy column 502 is input, 508 denotes a column selector connected to the normal columns 504, 509 denotes an amplifier circuit connected to the column selector 508 and the amplifier control circuit 507, and 510 denotes a row decoder connected to the memory array 500, respectively.
FIG. 16 shows a partial configuration of the memory array 500 shown in FIG. 15. In FIG. 16, reference numeral 511 denotes normal memory cells, and SRAMs are used often as the normal memory cells. Reference numeral 512 denotes edge cells included in the edge column 501, which is placed for avoiding the deformation of a physical pattern of the normal memory cells 511 at an edge portion of the array, and 513 denotes dummy cells included in the dummy column 502, respectively.
FIG. 17 shows a configuration of the memory cell 511 shown in FIG. 16, and FIG. 18 shows internal configurations of the edge cell 512 and the dummy cell 513 shown in FIG. 16 and an interconnection configuration therebetween.
As shown in FIG. 18, transistors constituting the edge cell 512 and the dummy cell 513 have the same size as that of transistors constituting the memory cell 511 shown in FIG. 17, and latch circuits included in the edge cell 512 and the dummy cell 513 are fixed at a constant level.
As shown in FIG. 16, the memory cells 511 are connected to word lines WL0 to WLx that are connected to the row decoder 510 in a row direction, and are connected to common bit lines BL and NBL in a column direction.
Among the plurality of edge cells 512, n edge cells 512 are connected to a dummy word line DWL on an output side of the dummy control circuit 505, and the other edge cells 512 are connected to a ground line. The n edge cells 512 have a configuration such that the n edge cells are arranged sequentially from a position closer to a side of the amplifier circuit 509.
Among the plurality of dummy cells 513, n dummy cells 513 are connected to the dummy word line DWL on the output side of the dummy control circuit 505, and the other dummy cells 513 are connected to the ground line. Furthermore, the plurality of dummy cells 513 are connected to the common dummy bit line DBL, and the dummy bit line DBL is connected to the amplifier control circuit 507. Similarly to the n edge cells, the n dummy cells 513 also have a configuration such that the n dummy cells are arranged sequentially from a position closer to a side of the amplifier circuit 509.
When the thus configured conventional semiconductor memory device operates, any one of the word lines WLO to WLx connected to the row decoder 510 is selected, and data in the memory cell 511 connected to the selected word line is read out onto the bit lines BL and NBL.
Note here that the bit lines BL and NBL and the dummy bit line DBL are precharged in advance to a high level so as to be in a floating state at the time when the word lines WL0 to WLx are selected. Furthermore, since there are a plurality of normal columns 504, data in a plurality of memory cells 511 connected to the selected word line are read out onto the respective bit lines BL and NBL, and data, in particular bit lines BL and NBL, are selected by the column selector 508.
At almost the same time the word lines WL0 to WLx are selected, the dummy word line DWL on the output side of the dummy control circuit 505 is driven, so that transistors constituting the n dummy cells 513 allow a signal level of the dummy bit line DBL to change from a high level to a low level at a slew rate that is n times that of the memory cell 511.
Then, the signal level of the dummy bit line DBL is detected, whereby the amplifier control circuit 507 generates an amplifier startup signal SAE, resulting in the amplifier circuit 509 amplifying data in the selected particular bit lines BL and NBL at a time when the amplifier startup signal SAE is input.
For example, in the case where it is attempted to start up the amplifier circuit 509 when a power supply voltage is 1.2 V and a potential difference between the read-out data (BL) and (NBL) from the memory cell 511 is 100 mV, if the number of the dummy cells 513 to be selected is set at “6”, the potential of the dummy bit line DBL changes to 600 mV, that is, to a half of the power supply voltage, at a desired amplifier startup timing. Therefore, there is an advantage that an amplifier startup signal SAE can be generated merely by using a simple CMOS gate and not using a complicated potential detection circuit.
In the above-described conventional semiconductor memory device, however, although wiring loads of the bit lines BL and NBL connected to the memory cells 511 are included in the dummy circuit, a load of the column selector 508 connected to the bit lines is not included in the dummy circuit. Therefore, there occurs a problem that the generation of a SAE signal based on a dummy bit line signal is delayed relative to the desired amplifier startup timing.
Furthermore, in the above-described conventional semiconductor memory device, the dummy cells 513 for driving the dummy bit line DBL are placed in the proximity of the amplifier circuit 509 with respect to the memory array 500. In the case where a memory cell 511 placed at an edge portion on an opposite side of the amplifier circuit 509 is selected, the delay due to the wiring resistance of the bit lines BL and NBL is not reflected, which means another problem that the generation of the SAE signal based on the dummy bit line signal is advanced relative to the desired amplifier startup timing.
Moreover, in the above-described conventional semiconductor memory device, the dummy cells 513 are configured so as to operate at every read-out access to the memory array 500, and such memory inherently has a problem that, in the case where the dummy cells 513 have a defect, the amplifier cannot be started up at the desired timing or such a defect may result in a defective product that is incapable of even starting up the amplifier.